The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for optimizing semiconductor packing in a three-dimensional stack.
Three-dimensional (3D) integration provides performance improvements for microprocessor architectures through the increased interconnectivity between tiers within the chip stack. However, the electrical off-stack connectivity (signals and power) is still implemented on only one surface of the chip stack and does not scale with the number of tiers. With further scaling of complementary metal-oxide-semiconductor (CMOS) transistors the number of C4s will not be sufficient even for single dies, due to the slow reduction in C4 pitch over time. For 3D chip stacks, this results in sever design constraints and reduces the performance gain possible from vertical integration.